## Parameters for MQDC-32


# I/O
# ############################################################################
# IO indices (ECL, NIM) always count from bottom (0) to top (3)
# ECL_term
0x6062  0b11000     # switch ECL/LVDS terminators on (1 -> on)
                    # Unconnected inputs will be in a well defined state by
                    # internal weak pull up resistors.
                    # +-----------+-------+-------+-------+-------+-------+
                    # | Bit       | 4     | 3     | 2     | 1     | 0     |
                    # +===========+=======+=======+=======+=======+=======+
                    # | ECL input | gates | gates | reset | gate1 | gate0 |
                    # | term.     | bank1 | bank0 | ECL1  | ECL2  | ECL3  |
                    # +-----------+-------+-------+-------+-------+-------+

# ECL_gate0  (ECL3) # Topmost ECL pin pair (below gnd pair) always Gate 0 when ECL selected

# ECL_gate1_osc(ECL2)
0x6064  0           # 0 -> gate1 input
                    # 1 -> oscillator input (also set CTRA.ts_sources (0x6096)!)

# ECL_fc_res (ECL1)
0x6066  1           # 0 -> fast clear input (= "not Gate")
                    # 1 -> reset time stamp counter
                    # 2 -> input for experiment trigger (since FW0110)

# Gate_select
0x6068  0           # 0 -> Gate 0 and 1 from NIM inputs
                    # 1 -> Gate 0 and 1 from ECL inputs

# NIM_gat0      (NIM 3); Topmost NIM connector always Gate 0 when NIM selected

# NIM_gat1_osc  (NIM 2)
0x606A  0           # 0 -> gate1 input
                    # 1 -> oscillator input (also set CTRA.ts_sources (0x6096)!)

# NIM_fc_reset  (NIM 1)
0x606C  0           # 0 -> fast clear input ( = "not Gate")
                    # 1 -> reset time stamp counter
                    # 2 -> input for experiment trigger (since FW0110)

# NIM_busy      (NIM 0)
0x606E  0           # 0 -> as busy (in independent bank operation:
                    #               active when both banks are busy)
                    # 3 -> as CBus output
                    # 4 -> buffer full
                    # 8 -> data in buffer above threshold 0x6018 (= Data Ready)
                    # 9 -> events in buffer above threshold 0x601E (since firmware FW0200)


# Internal Test Pulser
# ############################################################################
# pulser_status
0x6070  0           # 0 -> off
                    # 4 -> amplitude = 0
                    # 5 -> use pulser amplitude with 100 ns gate

# pulser amplitude
0x6072  32          # Pulser amplitude, typ. 32 for bin 2000
					# (max setting = 255)

# Timestamp/Event Counters: CTRA, CTRB
# ############################################################################
# ts_sources
0x6096  0b00        # bit 0: frequency source (0 -> VME, 1 -> external)
                    # bit 1: external reset enable

# ts_divisor (16 bit value)
0x6098  1           # timestamp = time / ts_divisor
                    # 0 means division by 65536


# Thresholds
# ############################################################################

# Individual channel thresholds. 12 bit values, 0 means the threshold is not used.
# 0x1FFF switches the channel off.
0x4000  0           # channel  0
0x4002  0           # channel  1
0x4004  0           # channel  2
0x4006  0           # channel  3
0x4008  0           # channel  4
0x400A  0           # channel  5
0x400C  0           # channel  6
0x400E  0           # channel  7
0x4010  0           # channel  8
0x4012  0           # channel  9
0x4014  0           # channel 10
0x4016  0           # channel 11
0x4018  0           # channel 12
0x401A  0           # channel 13
0x401C  0           # channel 14
0x401E  0           # channel 15
0x4020  0           # channel 16
0x4022  0           # channel 17
0x4024  0           # channel 18
0x4026  0           # channel 19
0x4028  0           # channel 20
0x402A  0           # channel 21
0x402C  0           # channel 22
0x402E  0           # channel 23
0x4030  0           # channel 24
0x4032  0           # channel 25
0x4034  0           # channel 26
0x4036  0           # channel 27
0x4038  0           # channel 28
0x403A  0           # channel 29
0x403C  0           # channel 30
0x403E  0           # channel 31

# ignore_thresholds
0x604C  0           # If set the threshold settings starting a 0x4000 are ignored (0 is assumed).


#***************************************************
#**************** ADVANCED MODES *******************
#***************************************************
# Operation Mode
# ############################################################################
# bank_operation
0x6040  0           # bit0: 0 -> banks connected
                    #       1 -> operate banks independently

# BANK OFFSETS
##############################################################################
# offset_bank0 (channels 0 to 15)
 0x6044 130         # Valid range is 0-255. Shifts the 4k spectrum by +-1000 bins.
#                   # Typical value: 130
# offset_bank1 (channels 16 to 31)
 0x6046 130         # Valid range is 0-255. Shifts the 4k spectrum by +-1000 bins
#                   # Typical value: 130
#                   # offset_bank1 also works for joined banks
# Note: Setting the offsets may take some milliseconds to take effect in the hardware.

# Gate Limit
# ############################################################################
# Refer to the lookup table at the end of the file for value - time conversion
# limit_bank0
0x6050  255         # 4 -> 4.5 ns, 255 -> no limitation
# limit_bank1
0x6052  255         # same as limit_bank_0

# Experiment Trigger
# ############################################################################
# Delay of experiment gate relative to end of QDC-gate [ns]. Up to 16384 ns (16k).
# exp_trig_delay0
0x6054  0           # delay for bank0 or both if joined banks
# exp_trig_delay1
0x6056  0           # delay for bank1 if not joined


#***************************************************
#**************** SPECIALS *************************
#***************************************************
# input coupling
0x6060  0b000       # bit0: bank0: 0 -> AC, 1 -> DC
                    # bit1: bank1: 0 -> AC, 1 -> DC
                    # bit2: 0 -> BLR on, 1 -> BLR off (since FW0114)

# skip_oorange
0x604A  0           # Skip out-of-range values

# Gate Limit Lookup table
# ###########
#setting 	time[ns]
#	4 		4,5
#	5 		4,6
#	6 		4,6
#	7 		4,7
#	8 		4,8
#	9 		4,8
#	10 		4,9
#	11 		5,0
#	12 		5,1
#	13 		5,2
#	14 		5,3
#	15 		5,4
#	16 		5,6
#	17 		5,7
#	18 		6,1
#	19 		7,6
#	20 		8,7
#	21 		9,4
#	22 		10,1
#	23 		10,9
#	24 		11,6
#	25 		12,3
#	30		16
#	35		19
#	40		24
#	50		32
#	60		41
#	70		51
#	80		62
#	90		73
#	100		86
#	110		101
#	120		117
#	130		136
#	140		158
#	150		185
#	160		219
#	170		268
#	175		300
