## Parameters for MDPP-16_QDC

# Operation Mode
# ############################################################################
# tdc_resolution									| Range
0x6042  0           # 0 ->  24 ps = 25 ns / 1024	| 1.6us
                    # 1 ->  49 ps = 25 ns / 512		| 3.2us
                    # 2 ->  98 ps = 25 ns / 256		| 6.4us
                    # 3 -> 195 ps = 25 ns / 128		| 12.8us
                    # 4 -> 391 ps = 25 ns / 64		| 25.6us
                    # 5 -> 781 ps = 25 ns / 32		| 51.2us


# first_hit
0x605C  1           # 0 -> transmit all hits per channel in the window
                    # 1 -> only transmit first hit per channel in the window

# Trigger Setup
# ############################################################################
# win_start
0x6050  $(16384 - 100 / 1.56) # second term: offset in ns, positive or negative
                    # Window of interest start time relative to trigger.
                    # Window start   = 16384  + delay[ns] / 1.56;
                    # Delay can be negative to register hits before the trigger.
                    # Delay may be in the range [-25560 ns, +25560 ns].
                    # < 0 -> window starts before trigger
                    # > 0 -> window is delayed

# win_width (14 bit value)
# ** the setting for tdc resolution should provide a time range larger or equal the window width 
# ** window dead time (minimum distance between two triggers)  = "width" + 500ns
0x6054  $(200 / 1.56)    # first term in ns;
                    # win_width = (win_width[ns] / 25ns * 16)
                    # max value 16383; (Hex notation: 0x3FFF)
                    # Range: [0, 25560 ns]

# trig_source
# Defines the trigger which creates the window of interest.
0x6058  0x100       # 0x001 -> trigger 0 input
                    # 0x002 -> trigger 1 input
                    # 0x100 -> whole bank (self trigger; all channels)
                    # single channel: trig_source = 128 + (chan * 4)
                    #                 with channel in 0..15
                    # +-------------+--------------------+---------+
                    # | Whole bank  |     16_channels    |  trig   |
                    # |   2 bits    |       6 bits       | 2 bits  |
                    # +============================================|
                    # |      0 | B0 | active | 0 | Chan  | T1 | T0 |
                    # |        |    |        |   | [3:0] |    |    |
                    # +--------+----+--------+---+-------+----+----+

# trig_source_2
0x605A  0           # When trig_source == 0, this register allows to set any
                    # number of individual channels to create the trigger.
                    # Bit 0 corresponds to channel 0, bit 15 corresponds to channel 15.
                    # Setting a bit uses the channel as a trigger source.

# trigger_output
# NIM1 trigger output
0x605E  0x100       # 0x100 -> whole bank (OR of all channels)
                    # single channel: trigger_output = 128 + (chan * 4)
                    #                 with channel in 0..15
                    # +-------------+--------------------+---------+
                    # | Whole bank  |     16_channels    |  trig   |
                    # |   2 bits    |       6 bits       | 2 bits  |
                    # +============================================|
                    # |      0 | B0 | active | 0 | Chan  | X  | X  |
                    # |        |    |        |   | [3:0] |    |    |
                    # +--------+----+--------+---+-------+----+----+


# I/O
# ############################################################################
# Sorted from top to bottom, as on the front panel.

# ECL3 input
0x6060  0x00        # 0x00 -> off
                    # 0x01 -> trig0, terminated
                    # 0x11 -> trig0, unterminated
# ECL2 input
0x6062  0x00        # 0x00 -> off
                    # 0x01 -> sync, terminated
                    # 0x11 -> sync, unterminated
                    # 0x02 -> trig1, terminated
                    # 0x12 -> trig1, unterminated
# ECL1 input
0x6064  0x00        # 0x00 -> off
                    # 0x01 -> reset, terminated
                    # 0x11 -> reset, unterminated
# ECL0 output
0x6066  0x00        # 0x0 -> off
                    # 0x4 -> busy
                    # 0x8 -> data in buffer above threshold 0x6018 (= Data ready)
                    # 0x9 -> events in buffer above threshold 0x601E

# NIM4 input
0x6068  1           # 0 -> off
                    # 1 -> trig0_in

# NIM3
# Note: Front panel Monitor setting overrides this setting (becomes mon1
# output).
0x606A  0           # 0 -> off
                    # 2 -> sync in (also set CTRA.ts_sources (0x6096)!)
# NIM2
# Note: Front panel Monitor setting overrides this setting (becomes mon0
# output).
0x606C  1           # 0 -> off
                    # 1 -> trig1_in
                    # 2 -> reset

# NIM1 is always trigger output

# NIM0
0x6074  1           # 0 -> off
                    # 1 -> CBus
                    # 4 -> busy_out (== FIFO full or ACQ stopped)
                    # 8 -> data in buffer above threshold 0x6018
                    # 9 -> events in buffer above threshold 0x601E

# Internal Test Pulser
# ############################################################################
# pulser_status
0x6070  0           # 0 -> off, 1 -> on

# pulser_amplitude
0x6072  400         # maximum amplitude: 0xFFF = 4095

# Timestamp/Event Counters: CTRA, CTRB
# ############################################################################
# ts_sources
0x6096  0b00        # bit 0: frequency source (0 -> VME-Sysclock, 1 -> external)
                    # bit 1: external reset enable

# ts_divisor (16 bit value)
0x6098  1           # timestamp = time / ts_divisor
                    # 0 means division by 65536

# stop_ctr
#0x60AE  0b00       # bit 0: stop CTRB (time_0, time_1, time_2)
                    # bit 1: stop CTRA (ts_counter_lo, ts_counter_hi)
                    # with 0 -> run, 1 -> stop counter
