# TRIVA registers:
# - Status Register     02000000 (hex)
# - Control Register    02000004
# - FCATIME             02000008
# - CTIME               0200000C

# Triva module initialisation as MASTER
# Write Control Register (0x02000004)
write A32 D32 0x0004 0x00000004         # MASTER - has to come first!
write A32 D32 0x0004 0x00001000         # disable trigger bus
write A32 D32 0x0004 0x00000010         # HALT
write A32 D32 0x0004 0x00000040         # CLEAR
write A32 D32 0x0008 $(65535 - 10)      # Fast Clear
write A32 D32 0x000C $(65535 - 20)      # Ctime

# Start_acq
write A32 D32 0x0004 0x00000010         # HALT
write A32 D32 0x0004 0x00000040         # CLEAR
write A32 D32 0x0000 14                 # Master sets Trigger 14
write A32 D32 0x0004  0x00000003        # (EN_IRQ | GO); Enable IRQ and send Trigger 14

# now ready to accept triggers -> after deadtime emits IRQ

######## MVLC setup for TRIVA triggering ########
# Optional signal aliases: map Triva trigger values to MVLC IRQs (1..15).
# Mapping a trigger value to 0 makes the MVLC ignore the trigger.

/*
writeabs A32 D16 0xFFFF7000 14  # TRIVA Trigger 14 (Start)
writeabs A32 D16 0xFFFF7002 14  # mapped to MVLC IRQ 14

writeabs A32 D16 0xFFFF7004 15  # TRIVA Trigger 15 (Stop)
writeabs A32 D16 0xFFFF7006 15  # mapped to MVLC IRQ 15

writeabs A32 D16 0xFFFF7008 1  	# TRIVA Trigger
writeabs A32 D16 0xFFFF700A 8  	# mapped to MVLC IRQ (data_event)

writeabs A32 D16 0xFFFF700C 2   # TRIVA Trigger
writeabs A32 D16 0xFFFF700E 9  	# mapped to MVLC IRQ (scaler_event)

writeabs A32 D16 0xFFFF7010 3	# Map trigger 3 (bit combination of 1&2) to the
writeabs A32 D16 0xFFFF7012 8	# data event too. This avoids the readout getting
                                # stuck when both the data and scaler triggers are
                                # active at the same time.

writeabs A32 D16 0xFFFF7020 14  # Map all other trigger values to the start event.
*/

/*
# All available signal alias registers:
# Mapping range 0 (since MVLC firmware FW0023)

writeabs A32 D16 0xFFFF7000 0      # triva trigger number
writeabs A32 D16 0xFFFF7002 0      # mapped to mvlc irq

writeabs A32 D16 0xFFFF7004 0      # triva trigger number
writeabs A32 D16 0xFFFF7006 0      # mapped to mvlc irq

writeabs A32 D16 0xFFFF7008 0      # triva trigger number
writeabs A32 D16 0xFFFF700A 0      # mapped to mvlc irq

writeabs A32 D16 0xFFFF700C 0      # triva trigger number
writeabs A32 D16 0xFFFF700E 0      # mapped to mvlc irq

writeabs A32 D16 0xFFFF7010 0      # triva trigger number
writeabs A32 D16 0xFFFF7012 0      # mapped to mvlc irq

writeabs A32 D16 0xFFFF7014 0      # triva trigger number
writeabs A32 D16 0xFFFF7016 0      # mapped to mvlc irq

writeabs A32 D16 0xFFFF7018 0      # triva trigger number
writeabs A32 D16 0xFFFF701A 0      # mapped to mvlc irq

writeabs A32 D16 0xFFFF701C 0      # triva trigger number
writeabs A32 D16 0xFFFF701E 0      # mapped to mvlc irq

# Mapping range 1 (since MVLC firmware FW0041)

writeabs a32 d16 0xFFFF7030 0      # triva trigger number
writeabs a32 d16 0xFFFF7032 0      # mapped to mvlc irq

writeabs a32 d16 0xFFFF7034 0      # triva trigger number
writeabs a32 d16 0xFFFF7036 0      # mapped to mvlc irq

writeabs a32 d16 0xFFFF7038 0      # triva trigger number
writeabs a32 d16 0xFFFF703a 0      # mapped to mvlc irq

writeabs a32 d16 0xFFFF703c 0      # triva trigger number
writeabs a32 d16 0xFFFF703e 0      # mapped to mvlc irq

writeabs a32 d16 0xFFFF7040 0      # triva trigger number
writeabs a32 d16 0xFFFF7042 0      # mapped to mvlc irq

writeabs a32 d16 0xFFFF7044 0      # triva trigger number
writeabs a32 d16 0xFFFF7046 0      # mapped to mvlc irq

writeabs a32 d16 0xFFFF7048 0      # triva trigger number
writeabs a32 d16 0xFFFF704a 0      # mapped to mvlc irq

writeabs a32 d16 0xFFFF704c 0      # triva trigger number
writeabs a32 d16 0xFFFF704e 0      # mapped to mvlc irq

# Catchall for signal aliases. Sets the mapped IRQ for all unassigned signal
# aliases (unassigned means never set or set to 0). Available since FW0026.
writeabs A32 D16 0xFFFF7020 0
*/
